Probabilistic delay fault model for DVFS circuits
نویسندگان
چکیده
منابع مشابه
A Probabilistic Model for Path Delay Fault Testing
Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we enter the deep submicron age. However, it is difficult in general since the number of faults is normally very large and most faults are either hard to sensitize or are untestable. In this paper, we propose a probabilistic PDF model. We investigate probability functions for the wire and path delay size to mode...
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ژورنال
عنوان ژورنال: Tsinghua Science and Technology
سال: 2011
ISSN: 1007-0214
DOI: 10.1016/s1007-0214(11)70058-x